Implementing probabilistic algorithms on VLSI architectures

In this paper, we pursue the use of probabilistic (randomized) algorithms in VLSI architectures, in order to reduce the amount of computation, and, correspondingly, the time of computation as well as chip area. As a case example, we propose two VLSI solutions to the well-known problem of the nearest pair of points in computational geometry. These implementations are based on Rabin's and Weide's probabilistic algorithms. The chip area and time of computation which result are each O(n). This is a marked improvement over both the straightforward deterministic approach (leading to an O(n z) computational time) and the deterministic algorithms known as being the best (leading to O(n log n) computational time). In suggesting a VLSI solution to the nearest-pair problem, we introduce two new systolic structures, a systolic grouper and a systolic minimum-distance processor. We also make use of a new class of systolic arrays introduced earlier, probabilistic systolic arrays.